1. Technical Field
This invention relates to the contact opening for pillar bumps in flip chip packages and, more particularly, to positioning the opening in an offset location to reduce the stress on the underlying integrated circuit.
2. Description of the Related Art
As integrated circuits become more dense, a larger number of contacts are made between the integrated circuit and the outside package based on the increasingly larger number of circuits contained in each integrated circuit chip. In addition to higher transistor packing density and more circuits on an integrated circuit die, the switching speeds are becoming much faster and lower power is being used. One of the reasons switching speed is becoming faster is the reduced capacitance in the intermetal dielectric layers. Currently, many low-k dielectrics are used between the metal layers which significantly reduces the capacitance and increases the speed of operation.
Most low-k dielectrics are constructed of a material which does not have the same mechanical strength as prior dielectrics used in the same locations. For example, many low-k dielectrics are made of nano porous material, aero gels, or other material which have a large number of air pockets therein. Since air has a dielectric constant of one, which is the lowest dielectric material available, the more air pockets which can be placed in the intermetal dielectric, the lower the dielectric constant will become and the faster the chip operation. Unfortunately, placing a large number of air pockets in the intermetal dielectric significantly reduces their physical integrity and strength. Prior to the use of significant low-k dielectrics, the various layers making up the integrated circuit had substantial structural integrity and had a hardness comparable to glass or silicon carbide. However, with the presence of many air pockets and nano pores in the low-k dielectrics, the material can be more easily crushed and, if too much stress is placed on the top surface of the package, the dielectric layers will crack or collapse, thus causing failure of the integrated circuit. It is therefore beneficial to reduce, whenever possible, the amount of stress which is placed on the integrated circuit in order to reduce the likelihood of crushing, cracking, or otherwise damaging one or more of the intermetal dielectric layers of the integrated circuit.